In the field of manufacturing dynamic random access memories (DRAMs), the storage capacitor is formed as a deep trench capacitor within the semiconductor substrate. The lower portion of the trench comprises the storage node having one plate of the capacitor within the substrate, having the dielectric layer arranged on the sidewalls of the lower portion of the trench and having the second electrode arranged preferably as a polysilicon filling material within the trench. The upper portion of the trench is isolated from the substrate by a so called collar isolation, preferably a thick silicon oxide collar layer. In the sequence of process steps for the manufacturing of the trench capacitor, the semiconductor wafer is provided with the storage node already completed. At this point, the lower portion of the trench has the dielectric layer arranged on its sidewalls and is filled with polysilicon. On the surface of the wafer, a PAD-silicon nitride layer is already deposited. The upper portion of the deep trench is still open and subject to further processing. Now, a conformal isolation layer, preferably a silicon oxide layer, is deposited on the wafer. As a result, the conformal layer of silicon oxide is present on the sidewalls of the upper portion of the trench, on the bottom surface of said upper portion of the trench, and on the silicon nitride layer on the main surface of the semiconductor wafer. Within the upper portion of the trench, the silicon oxide layer is directly deposited onto the upper end of the polysilicon filling material, which is arranged in the lower portion of the deep trench. At this stage, the process of manufacturing the trench capacitor continues with the removal of the horizontal portions of the conformal silicon oxide layer, e.g the portions being arranged on the bottom of the upper portion of the deep trench. As a result, the vertical portions of the silicon oxide layer remain on the sidewalls of the upper portion of the deep trench as a collar isolation in order to electrically isolate the further filling of the upper portion of the deep trench from the surrounding substrate of the semiconductor wafer. The bottom of the upper portion consisting of, e.g., silicon oxide is opened to ensure the electrical accessibility of the polysilicon in the lower portion of the trench. At a later phase of the manufacturing process of a DPAM device, an active area comprising an access transistor is formed within the substrate adjacent to the collar isolation.
The opening of the bottom surface of the trench must be performed without damaging the silicon nitride layer. For such removal of silicon oxide, a dry etch process using the etch gas C4F8 is already known. The etching with C4F8 provides sufficient selectivity between silicon oxide and silicon nitride on the surface of the wafer and moreover provides a good etch stop performance on the bottom of the trench versus the polysilicon filling material. A disadvantage of the etch gas C4F8, however, is that the very top section of the vertical part of the collar oxide is also etched to a larger extend due to the high silicon oxide etch rate of C4F8. This is particular true when used in capacitively working plasma etch chambers, where a high sheath voltage causes a high ion energy acceleration to the wafer surface which results in a high oxide etch rate. As a consequence said very top vertical section of the collar oxide may be recessed to such an extend that the silicon oxid (PAD-oxide) hidden behind the collar oxide underneath the PAD-nitride subsequent process steps. One of the subsequent process steps is an isotropic silicon wet etch which can undercut the PAD-silicon nitride layer. The reliability of the process is less stable and the production yield for DRAM devices is lower.
It is an object of the invention to provide a more stable and more reliable process of forming an isolation layer on the sidewalls of a trench. It is a further object of the invention to provide a more stable and more reliable method of manufacturing a trench capacitor having such an isolation layer.
According to the invention, a method of forming an isolation layer on the sidewalls of a trench can include providing a semiconductor wafer comprising a substrate having a first isolation layer stack arranged on a main surface of the substrate and having a trench arranged in the substrate; depositing a second isolation layer on the wafer; etching the wafer in a first step with a first etch gas composition comprising the gases CF4 and SiF4 and O2; and etching the wafer in a second etch step subsequent to the first etch step with a second etch gas composition comprising the gas C4F8.
A method of manufacturing a trench capacitor, as described above can include a semiconductor wafer including a deep trench having a lower portion with a dielectric layer arranged on its sidewalls and being filled with silicon and having an upper portion being arranged above the lower portion with the second isolation layer being deposited on the sidewalls of the upper portion of deep trench, and on the surface of the silicon arranged within the lower portion of the deep trench, and on the surface of the first isolation layer stack.
The methods according to the invention benefit from a twostep etch process for the removal of the horizontal portions of the second isolation layer so that only the vertical portions remain, thereby forming a reliable collar oxide within the trench capacitor. The two steps of the etch process have different properties that are adopted to the progressing of the overall etch procedure. In this respect, the first etch step comprises a gas composition of CF4, SiF4, and O2. This etch gas composition is known to etch silicon oxide, silicon nitride, and polysilicon at substantially the same rate, e.g., without substantial selectivity to each other. The etch rate of silicon oxide on the top of the wafer can be adjusted to be rather low. There is only little removal of silicon oxide on the top surface of the wafer so that it can be assured that there is always a sufficiently thick silicon oxide layer on the silicon nitride layer that protects the silicon nitride. At the bottom of the trench, the etch rate of silicon oxide is rather reasonable so that the silicon oxide is frilly removed from the underlying polysilicon filling material. As a result of the first etch step using CF4, SiF4, and O2, the silicon oxide on the bottom of the trench is removed whereas a thin silicon oxide layer is still present on the top main surface of the wafer protecting the silicon nitride. Moreover, the very top section of the vertical collar oxide is not damaged. The different etch rates for silicon oxide on the bottom of the trench and on the top surface are due to the fact that there is etching and deposition of silicon oxide on the top surface and the trench bottom at the same time. At the trench bottom, the removal of silicon oxide dominates strongly over the deposition of silicon oxide, whereas at the top surface the removal dominates only slightly over the deposition resulting in a higher overall oxide etch rate at the trench bottom than at the top surface.
In the second etch step, the etch chemistry C4F8 which is preferably diluted with CO or alternatively CO and O2. This chemistry is known for substantially high selectivity between silicon oxide and silicon nitride so that the thin layer of silicon oxide that was left at the end of the first etch step can be etched away in a rather uniform way without damaging the underlying silicon nitride layer. It is to be noted that the vertical portion of the silicon oxide layer at the very top of the collar is recessed during the second etch step, due to the aggressiveness of the etch gas with respect to silicon oxide. The amount of recess, however, can be tolerated and is clearly within the thickness of the silicon nitride layer and does definitely not reach below the silicon nitride layer. The silicon substrate that is to be protected by the collar oxide is, therefore, sufficiently covered at the very top portion of the trench where the silicon substrate contacts the silicon nitride layer so that there is no undercut by subsequent application of wet etch chemicals.
As an overall consequence, the collar etch combines the advantages of C4F8 and CF4/SiF4/O2 etch properties for the etching of the collar oxide for the manufacturing of a trench capacitor. As a result, a defined nitride surface is provided on the top of the wafer having good uniformity of the nitride layer, the collar oxide is only recessed little at the trench top and the collar oxide at the trench bottom is opened perfectly.
The first etch step using CF4/SiF4O2 chemistry is finished when the silicon oxide is completely removed from the bottom of the trench. The second etch step using C4F8 chemistry is finished when the silicon oxide on top of the wafer, i.e., on top of the silicon nitride, is completely removed. The first etch step is run by time or endpoint while the second etch step is finished by endpoint. The second etch step employs a polymerizing chemistry. It is therefore advantageous to introduce a subsequent sputter etch with O2 to remove probable polymer residues which is preferably followed by a wet etch clean.
As already stated, the isolation layer on the vertical sidewalls of the trench are particularly useful for a collar isolation oxide layer which isolates the upper part of a trench capacitor. The upper portion of the overall deep trench capacitor which is subject to the aforementioned etch processes serves to isolate the subsequent polysilicon filling of the trench from the surrounding silicon substrate where the active areas including access transistors are subsequently formed. The lower portion of the trench capacitor serves as the storage node comprising the two electrodes of the capacitor.